This invention is generally related to forming connections between layers in a semiconductor structure, and more particularly to an improved conductive via formation technique that utilizes a Platinum group metal or alloy on a second Tantalum Nitride layer within the via opening.
Copper interconnect technology is running up against significant limitations in satisfying conflicting demands of good Copper full quality, current redundancy in the liner metal, good barrier properties against Copper diffusion (particularly with respect to integration with low-K dielectrics), and cost-effectiveness, manufacturability and compatibility with proven deposition technologies.
To address these issues, the embodiments of the invention provide a method that patterns at least one opening in a low-K insulator layer of a multi-level integrated circuit structure, such that a copper conductor is exposed at the bottom of the opening. The method then lines the sidewalls and the bottom of the opening with a first Tantalum Nitride layer in a first chamber and forms a Tantalum layer on the first Tantalum Nitride layer in the first chamber.
Next, sputter etching on the opening is performed in the first chamber, so as to expose the conductor at the bottom of the opening. The sputter etching can comprise, for example, an Argon sputter etchback. The sputter etching leaves a portion of the first Tantalum Nitride layer and a portion of the Tantalum layer on the sidewalls of the opening. While the structure is still in the first chamber, a second Tantalum Nitride layer is formed on the conductor, the sidewalls, and on the remaining portions of the Tantalum layer and the first Tantalum Nitride layer.
After the second Tantalum Nitride layer is formed, the methods herein move the structure to a different chamber (second chamber) and form a flash layer comprising a Platinum group metal on the second Tantalum Nitride layer. The Platinum group metal comprises at least one of: Ruthenium, Rhodium, Palladium, Osmium, Iridium, and Platinum. After this processing, the structure can be moved to a third chamber where copper is deposited, or seeded, on the flash layer in the opening until the opening is coated with a copper seed layer in the third chamber. After the deposition of the copper seed layer, the wafer would then be removed from the vacuum system and electroplated with copper so as to fully fill the via and line structures with copper. The plasma vapor deposition (PVD) seed layer followed by electroplating of the copper metals creates an electrical connection between the conductor and a second conductor on an opposite side of the insulator layer.
These and other aspects of the embodiments of the invention will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings. It should be understood, however, that the following descriptions, while indicating preferred embodiments of the invention and numerous specific details thereof, are given by way of illustration and not of limitation. Many changes and modifications may be made within the scope of the embodiments of the invention without departing from the spirit thereof, and the embodiments of the invention include all such modifications.